Analog Layout Engineer (Lead)

Kandou AI · IT

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AvailableFull TimePosted Sep 13, 2026

Source: Arbeitnow

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Category
IT
Employment type
Full Time
Experience level
Lead

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Original employer: Kandou AISource ATS: ArbeitnowJob status: Active

Kandou AI is looking for a Lead Analog Layout Engineer to work on high-speed chip-to-chip communication links. This role is fully remote within the EU, Switzerland, and the UK.

The Lead Analog Layout Engineer will be responsible for the custom layout and verification of analog circuits for multi-Gigabit SerDes and memory IOs. The role involves close collaboration with design teams and customers to ensure the successful delivery of high-performance semiconductor IP. Candidates will focus on advanced semiconductor nodes and utilize sophisticated EDA tools for signal integrity, parasitics extraction, and circuit validation.

Why You’ll Love This Role

Location restricted to EU, Switzerland, and UK
Senior leadership level role
Focus on AI memory fabric infrastructure
Semiconductor physics engineering focus
Full remote flexibility

What You’ll Bring

Experience in custom analog layout for multi-Gigabit serial data-link transceivers or HF/RF circuits
Expertise in layout of high-speed frequency circuits like amplifiers, oscillators, PLLs and DLLs
Understanding of high-speed circuit layout approaches and parasitics minimization
Proven experience on 28nm, 14/16nm, or 7nm semiconductor process technologies
Proficiency with EDA tools including Cadence Virtuoso, Spectre, and Calibre
Graduate degree in Electrical Engineering

What You’ll Get

Benefits not specified in the listing

About the Company

Kandou AI focuses on democratizing AI by reducing the total cost of ownership for hardware systems through proprietary MIMO-over-copper technology. They specialize in high-performance, energy-efficient, chiplet-based AI memory fabrics designed to scale AI training and inference.

Listing checked for remote eligibility · Posted Sep 13, 2026 · ArbeitnowApply
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